This paper describes the use of a C language-based design methodology to implement a GSM baseband processor on a TMS320C6201 DSP and on an FPGA. The following section presents an overview of GSM with an emphasis on the details of Layer 1. The GSM overview is followed by a discussion of behavioral modeling that is used to develop the baseline algorithms. Following this is a description of the TMS320C6201 and Xilinx Virtex FPGA implementations.