FPGA Implementation of a DSP Core for GSM Vocoders
The Global System for Mobile (GSM) communications uses a 13-Kbps vocoder, which expands to 22.8 Kbps after channel coding. The computational requirements of such a vocoder and of other necessary services requires the design of an entirely new digital signal processing (DSP) architecture geared towards 1-D signal and speech processing. This paper suggests a hardware core for speech coding applications that is implmented on an (FPGA) and can do 16-bit, fixed-point operations. Pipelining and parallel operation based on the specification for GSM vocoders are used.
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