Verifying designs for FPGA implementation requires a set of tasks and tools unique to the technology. Unlike designs destined for an ASIC, standard cell or custom implementation of an FPGA design does not generally have extensive resources allocated and preparation devoted to design verification. In many cases verification is more of an afterthought due to the ability to reprogram the device. This paper will consider the tools and techniques that may be used in the course of a verification cycle and will examine the benefits and shortcomings of each.