Foundation IP for 7nm FinFETs: Design and Implementation
Learn about the challenges of IP design and implementation for 7nm FinFETs. Along with the performance and area benefits that the node brings, designers must understand the significant technical challenges stemming from increasing variability associated with tighter pitches and more complex lithography steps. Design for variability and reliability considerations will require comprehensive modeling and analysis as well as advanced circuit techniques such as on chip sensing and compensation.
Please disable any pop-up blockers for proper viewing of this Whitepaper.