Flexible and Adaptive On Chip Interconnect for Terascale Architectures
Tera-scale architectures represent a set of designs that enable high levels of parallelism to address the demands of existing and mostly emerging workloads. This paper presents the design of an on-chip interconnect with aggressive latency, bandwidth, and energy characteristics that is also flexible and adaptive. This paper also covers the design choices and policies within the constraints of an on-chip interconnect and demonstrate the effectiveness of these choices for different usage scenarios.
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