FPGA design sizes and complexity are now in the stratosphere. An increasing number of designers are struggling to meet their design goals in a reasonable amount of time.

Xilinx introduced PlanAhead software as a means to combat lengthening design closure times. The PlanAhead hierarchical design and analysis tool helps you quickly comprehend, modify, and improve your designs. Earlier PlanAhead versions (7.1 and earlier) were used to improve performance of the design through floorplanning. The software does encapsulate Xilinx ISE back-end tools to complete the EDIF/NGC-to-bitstream flow. However, earlier versions left the complex job of design closure through place and route options to the user.

Reprinted with permission from Xcell Journal / Third Quarter 2006. Article © Xcell Journal.