Executing an RTOS on Simulated Hardware using Co-verification
Hardware software co-verification tools allow a designer to run software against a hardware design before a prototype has been built. They accomplish this by executing the software on a logic simulation of the hardware design. However, logic simulations are notoriously slow, typically running at about 1 to 10 clock cycles per second on complex designs. Co-verification tools mitigate this slowness by running only a small fraction of the bus cycles generated by the software against the simulated hardware. Most bus cycles, such as data references and instruction fetches, are executed against a simple memory array. This runs much faster and reduces the workload on the logic simulator. One consequence of this is that the “hidden” bus cycles are run without advancing time as far as the logic simulator is concerned. A problem occurs when the hardware has elements that depend on the clocks for proper operation, such as timers and counters.
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