Today’s networking boxes require clock generation and buffering. Traditional methods involved a clock oscillator and a clock buffer. For LAN applications, a typical 156.25-MHz clock is needed, and for WAN applications a 155.52-MHz clock is used. Due to the low jitter and accuracy needed for these clock oscillators, their cost are high. So how does a designer lower cost but maintain low jitter, high accuracy, and clock buffering in a single solution?