Estimating Clock Tree Jitter
High speed, high performance timing applications often require a combination of oscillators, clock generators, clock buffers and jitter cleaning clocks to satisfy system timing requirements. Each component in the clock tree adds phase jitter to the starting reference clock. One question that arises is how to estimate the total clock jitter through the clock tree to ensure there is adequate system-level margin to reliably meet the application jitter requirements. By ensuring jitter design targets are properly met, system timing related problems can be avoided. This application note discusses three common approaches to estimate total clock tree jitter with the focus on additive jitter when using a clock buffer.
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