ESL Tools Make FPGAs Nearly Invisible to Designers
FPGA business dynamics have been rather consistent over the past decade. Price per gate has continued to fall annually by an average of 25%, while device densities have continued to climb by an average of 56%.
Concurrent with advances in silicon, design methodologies have also continued to evolve. In particular, a new paradigm known as electronic system level (ESL) design is promising to usher in a new era in FPGA design. Although the term ESL is broad and its definition subject to different interpretations, here at Xilinx it refers to tools and methodologies that raise design abstraction to levels above the current mainstream register transfer level (RTL) language.
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