As both designs, and the FPGAs used for these designs, have grown into the millions of gates, FPGA designers are adopting more ASIC design processes, verifying the design with simulation at each step. But as the designs have grown larger, simulation runs have increased greatly. These large FPGA designs demand the verification tools used for ASIC design to minimize the time required for verification without compromising the coverage.

This paper describes the FPGA design verification process, starting with a design synthesized with Precision RTL and verified using the FormalPro Equivalence Checker. This verification flow can greatly improve FPGA design productivity, avoiding days of constraint creation, orders of magnitude faster than gate-level simulation with 100% RTL/netlist coverage.

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