The growing demand for ultra-low power ICs in the area of connected and mobile devices is driving the adoption of the FinFET technology node at 16-nanometers (nm) and below for system-on-chip (SoC) designs. While a smaller footprint, higher performance and lower leakage are key benefits with FinFETs, reliability in terms of thermal, electromigration (EM) and electrostatic discharge (ESD) are major challenges. While reliability is a “sign-off” item, it must be addressed during the design phase if time-to-market is as critical as power-efficiency, smaller footprint, higher performance and lower cost. This paper addresses the above issues.