As FPGAs have evolved from their early stages, the goal of dynamic partial self reconfiguration, where one or more functions can be modified while the remainder of FPGA functionality remains operational (analogous to multi-threading of a general purpose processor) has always been within grasp. With the advent of the high performance FPGA platforms with embedded PowerPC cores, dynamic partial reconfiguration is now a reality. This paper demonstrates this capability and emphasizes key embedded processor responsibilities in partial reconfiguration.