As the semiconductor technology migrates to 0.13 micron and below, it is becoming increasingly clear that test sets for single stuck-at faults alone are not sufficient to achieve the required quality levels. At 0.13 micron and below, circuits are more susceptible to speed related defects and hence to attain good quality, at-speed test sets such as those based on transition and path delay faults are necessary. While these additional test sets improve the test and product quality, they further exacerbate the problem of rising test data volume and test application time. Even test sets for single stuck-at faults for the current multi-million gate designs exceed the tester memory capacity. In addition, due to the bandwidth limitation they result in increased test application time. The variety of software test set compression techniques employed by the present automatic test pattern generation (ATPG) tools alone is not enough to solve the escalating test data volume and test application time. It is necessary to employ an efficient and effective hardware compression technique that not only reduces the cost-of-test by reducing the test data volume and test application time, but also maintains and/or improves the quality levels. This publication discusses a novel, breakthrough DFT technology called Embedded Deterministic Test (EDT) that provides dramatic reduction of test data volume and test application time while maintaining the quality levels achieved by the current scan/ATPG methodology. EDT is an integral part of TestKompress, a Mentor Graphics tool for compressed ATPG. An alternative, less effective technique proposed in the literature to contain the cost-of-test through test data compression is also presented. It becomes clear from the discussion that EDT, with no performance impact, little area overhead and minimal impact to the flow, results in a scalable and significant reduction of scan test data volume and scan test time while maintaining high test quality levels.

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