Emerging from a host of competing technologies, DDR2 and DDR3 SDRAM (“DDR”) have become the dominant off-chip memory storage solution for system-on-chip (SoC) designs. With high volumes driven by the PC market, stability of supply, and attractive pricing, DDR has defeated all of the contenders including QDR SRAM, RLDRAM, Rambus DRAM and other memory technologies to take the RAM crown for embedded applications. Unfortunately, many SoC designers are unfamiliar with the realities of the DRAM standards, typical DRAM applications and the DRAM market. This paper presents ten guiding principles for embedded DDR interfaces, many of which the DRAM standards and vendor data sheets do not explain.