Increased susceptibility of system integrated circuits (ICs) to electrostatic discharge (ESD) and increasingly stringent signal integrity requirements are leading to fundamental changes in ESD protection strategies at the system design level.


The traditional approach to dealing with higher data rates has been to reduce the capacitance of the ESD protection device; this tends to reduce the ESD protection capabilities of the device, forcing designers to make tradeoffs between system reliability and signal integrity. This paper introduces an innovative ESD protection architecture created by California Micro Devices (CMD) that eliminates the tradeoff between signal integrity and ESD protection. The paper also discusses various topics related to ESD protection, including device trends, shortcomings of traditional ESD protection architectures, and important considerations for choosing an ESD protection device for superior signal integrity.