Semiconductor companies have traditionally supported design flows that incorporate a wide range of EDA tools from many different vendors. By choosing best-in-class tools for specific sections of the design flow, CAD teams can create an environment that allows designers to complete projects on schedule. However, because physical verification is the common thread throughout a design, from layout to silicon, employing multiple physical verification tools can create discontinuities that result in errors, delayed tape-out, manufacturing problems, and missed time-to-market windows.

Supporting separate tools for interactive (cell/block) and batch (large block/full chip) physical verification also requires duplication in training, rules files, documentation, support, software installation and maintenance. Scarce CAD resources will be further strained by the need to gain expertise in and support duplicate tools.

Choosing a single, robust, hierarchical-based tool for both interactive cell/block and batch/full-chip/sign-off verification ensures a confident design while saving time and resources. When that single tool is the internal standard at the foundry, engineers can be assured there will be strong coverage for future process rule files.

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