High performance analog IC relies on special layout techniques to achieve the maximum speed with the lowest power. Electro-migration (EM) is a large concern in any analog circuit but especially for high speed parts. The scope of this paper is to introduce some techniques that make the EM check part of the standard post-layout simulation flow by eliminating the side effect of post-simulation to make it scalable with the design and easy to implement in any technology. Because the EM check requires that the simulation run in the presence of millions parasitic components, some Eldo special options for R reduction are also introduced, along with some suggestions on how to use them. The overall flow was successfully tested on a netlist having 1.2M parasitic resistors by running OP, transient analysis and an EM check.

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