The Easy Steps to Calculate Sampling Clock Jitter for Isolated, Precision High-Speed DAQs
Many data acquisition (DAQ) applications require an isolated DAQ signal chain path for robustness, safety, high common-mode voltage, or to eliminate ground loops that can introduce an error into a measurement. Precision, high speed technology enables system designers to achieve high AC and DC accuracy with the same design, without having to trade off DC accuracy for higher sampling rates. However, to achieve high AC performance, such as signal-to-noise ratio (SNR), system designers need to take into account the error introduced by jitter on the sampling clock signal or convert-start signal that controls the sample-and-hold (S&H) switch in the ADC (analog-to-digital converter). Jitter on the signal controlling the S&H switch becomes a more dominant error as the signal of interest and sample rates increase.
This paper explains how to interpret the jitter specifications on LVDS (low-voltage differential signaling) digital isolators and which specifications are important when interfacing to precision, high speed products.
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