Early Defect Discovery with Assertion-Based Verification Accelerates Design Closure
When designing a system-on-chip (SoC) using a platform FPGA for mobile, wireless, networking, or media applications, designers typically integrate many IP components within a short period of time. By offering advanced Xilinx® MicroBlaze™ and onchip PowerPC™ processors, platform FPGAs such as the Virtex™-II Pro and Virtex-4 families give you a head start on integrating processor IP.
Regardless of your IP choice, market requirements are driving the need for more features, such that processor-based platform designs are becoming more complex—incorporating multiple processor cores and multi-layered bus architectures. This spiraling increase in complexity drives the need for new approaches to platform FPGA design and verification. The simple, push-button flow of synthesis logic mapping, with verification as an afterthought, just doesn’t cut it.
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