Capturing the designer’s intent during floorplanning plays a critical role to improve design productivity of systems-on-chip (SoC). This paper presents a design technique which helps manage changes very late in the design process caused by the concurrent implementation of blocks in a hierarchical layout.

We developed a floorplan description language and associated a methodology to capture the actual designer’s intent for block placement, soft macro shaping, JTAG cell placement, power grid and power rings design.

The concept allows re-use of the description and therefore fast iterations during incremental changes at the top level or at the block level. This technique can accommodate changes very late in the design process by removing tedious manual adjustment of the hierarchical layout.

This approach has successfully been applied on a complex SoC and IP block implementation. It has demonstrated a reduction from one day to few minutes for a floorplan iteration, crucial in a concurrent design environment where asynchronous changes in the blocks require to constantly revisit the top level layout and vice versa.

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