Clock switching is a large source of power used in digital circuits, especially in high-speed designs. As power consumption becomes increasingly important, designers are looking for more ways to reduce unnecessary switching inside chips. One method is turning off the clocks to specific portions of the circuit when not in use. Not only does this save the power used in clock switching, but also power used in logic and I/O switching. Devices in the QuickLogic PolarPro family, QL1P200 and larger, provide a powerful dynamic clock disable feature that allows designers to turn clocks going into the QuickLogic chip on and off, on the fly. Built-in deglitching circuitry prevents clock glitching during transitions so that clocks can be enabled or disabled asynchronously. This enables efficient power management schemes to be implemented easily and quickly. This paper discusses the dynamic clock disable feature in detail, outlines steps to implement this feature, and shows simulations of a design example using this feature.