DS33R41 Multichip-Module BSDL Testing
This application note describes how to alter the printed wiring board (PWB) netlist of a design containing the DS33R41 Inverse-Multiplexing Ethernet Mapper with Integrated Quad Port T1/E1/J1 Transceiver so that the netlist complies with the Joint Test Action Group (JTAG) specifications. These changes are necessary because the DS33R41 was designed as a multi-chip module with multiple die in a single package which can not be defined by the Boundary-Scan Description Language (BSDL) for board level JTAG testing. The application note contains external pin mapping tables, internal die pad bond tables, and connection information allowing the designer to quickly achieve accurate JTAG boundary-scan board testing.
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