In the nanometer era, physical verification is no longer just a pass/no pass routine. It has evolved into a whole new way of ensuring comprehensive analysis, incremental verification, efficient debugging and improved cycle times. It is about using intelligent DRC (Design Rule Check) tools that manage the bumps in the road and make the best use of hardware configurations, as well as about making best use of designer’s time. This paper describes the evolution and new functions of DRC, and explains how run-time and debug time can be reduced and translation time eliminated.

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