A simple methodology to predict transistors performances due to systematic lithography and etch effects is presented. It is based on physical silicon simulation, followed by device modeling, incorporated in the silicon simulation software. This method enables an easy and efficient analysis of device parameters with the same simulation tool usually used for process analysis. The method is demonstrated on small and large arrays of standard cell blocks, designed for TS013SL (0.13┬Ám Standard Logic for General Purposes) Platform. Electrical parameters, like drive current (Idsat), and Off current (Ioff) were predicted. Comparison between different transistors types, having the same W/L but different layout configuration and various layout environments (around the transistor) was made in terms of performances as well as process variability.
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