Developing an Effective Methodology for Checking RTL
Many of today’s large, complex designs contain thousands of lines of Verilog or VHDL code, developed by teams of engineers, often located at multiple locations worldwide. As a simple mistake in just one line of code can cause a schedule delay while the issues is debugged, it is crucial that code is checked against coding standards and best practices during development. In addition, it is important for the team to follow a common methodology for checking all source code to ensure that errors are caught early in the design process.
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