“At-speed testing” of any device for reliable operation at the rated frequency is an essential part of the testing process; it contributes significantly in lowering Defective Parts Per Million (DPPM) seen by the customer. This paper describes the motivation and methodology for ensuring full quality of at-speed testing in any design with multiple operational frequencies. Absence of this verification methodology can lead to over-testing or under-testing of certain clock domains and hence inadequate at-speed testing.