DesignWare SATA AHCI Host Controller
This paper describes how to configure and connect the DesignWare SATA AHCI IP core to the Synopsys PHY in a multi-port AHB-based configuration, and provides an analysis of the expected throughput on each port based on assumed system parameters. The expectation is that a user should be able to take this example and insert actual system parameters to come up with a performance estimate. We will look briefly at the architecture of the core to enable a better understanding of the subsequent sections describing the configuration and performance calculations of the core. Also, note that while this document only discusses the performance of an AHB-based configuration, the option to select an AXI-based configuration will be available in the near future. Due to the nature of the AXI-bus, which allows for overlapping transfers, we expect an increase in the performance of a multi-port configuration.
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