Dynamic reconfiguration of hardware components is a well-established technique that is very familiar to most systems architects and designers. An FPGA that is dynamically reconfigurable is capable of being partially reconfigured while operational without compromising the integrity of the applications running on those parts of the FPGA that are not being reconfigured. Designers have reported many reasons why the ability to time multiplex hardware dynamically on a single FPGA is advantageous. These include applications as diverse: as reducing the size of the FPGA required for implementing a given function with consequent reductions in cost and/or power consumption; improving FPGA fault tolerance; and thermal monitoring of the FPGA die.


This paper describes new architectural enhancements to Xilinx FPGAs that better
support the creation of dynamically reconfigurable designs. In addition, a new design methodology is presented that uses pre-routed IP cores for communication between static and dynamic modules. It introduces a new capability that permits nets associated with the static portion of a design to be routed through regions in which the logic is reserved
exclusively for implementing dynamic modules. The combination of new architectural features, new IP cores, an improved design methodology and supporting CAD tools makes the process of designing dynamically reconfigurable systems with industrial quality devices and tools much more accessible.