The need for higher performance applications is driving the requirement for a new age of on-chip communication infrastructure. Increasing the clock frequency no longer addresses this higher performance requirement, as the bottleneck is inherent in the existing bus infrastructure.

This paper examines the advantages of the new AMBA 3 Advanced eXtensible Interface (AXI) protocol for on-chip bus infrastructure, and how it revolutionizes the future of high-performance system-on-chip (SoC) interconnect. It describes the AMBA 3 AXI protocol feature set that makes it suitable for the new high-performance, low-latency, and low-power designs. It also examines the verification tools and intellectual property (IP) necessary to successfully complete design and verification in today’s reduced development design cycle.