Designing with Intel components allows a lot of power management flexibility. One of the down sides of this flexibility is the need for independent power supply wells driving the chip. A large number of embedded customers do not require this flexibility and therefore are sacrificing cost and board space. If the rails are not needed, adding them does not provide a positive return on investment. For example, if the chip requires a 3.3V_main power rail and a 3.3V_standby power rail. This paper focuses on how to collapse these into a single power rail. For the purposes of this paper, this concept will be referred to as "associated power rails".