Designing Scalable 10G Backplane Interconnect Systems Utilizing Advanced Verification Methodologies
The design and implementation of high-speed backplanes requires substantial effort both in pre-prototype modeling and post-prototype testing and measuring. Extant methods for modeling backplane signal paths have become very sophisticated and time consuming. Correspondingly, current test methods for verification of design have relied on direct measurement techniques which are often useful for only a single test condition requiring multiple test runs. This paper presents techniques for design which significantly reduce modeling requirements for the design of high-speed backplanes in conjunction with advanced testing techniques which provide maximum channel characterization with the minimum amount of time.
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