This white paper discusses how structured ASICs can be used as an affordable, fast time-to-market solution to address the high costs and risks of complex 90nm system-on-a-chip (SoC) developments. A business case is presented for a fabless design house that considers the development of a multi-protocol CDR/SerDes-based SoC supporting PCI Express, SGMII, and 10GbE/XAUI interfaces. The paper analyzes the expenses and associated cash flows of the life cycle of the SoC and demonstrates how both fabless and system OEMs can use structured ASICs as a smart market entry strategy to reduce design risks and development costs, helping companies to better focus their resources on value-added, differentiating IP developments.