The increase in FPGA densities is giving rise to more than just substantially larger logic arrays. Today’s FPGA designs incorporate an increasing amount of tightly integrated hard IP blocks—a trend that creates new challenges for design software. One of the most critical challenges is the difficulty of traditional logic synthesis tools to correctly predict the critical path of the design as geometries shrink and wire delays become predominant.

The latest advances in logic synthesis now make it possible to use the integrated DSP blocks of Xilinx® Virtex™-4 FPGAs at their full potential. Physical synthesis has emerged as the key new technology to reconcile the RTL optimization effort with performance bottlenecks seen at the placement stage.

In this article, I’ll consider these and other new software challenges posed by state-of-the-art FPGAs, and how Xilinx and its software partners Synplicity and Mentor Graphics are responding.

Reprinted with permission from Xcell Journal / Fourth Quarter 2005. Article © Xcell Journal.