The advent of FinFET-based memories presents new memory test challenges. This white paper covers the new design complexities, defect coverage and yield challenges presented by FinFET-based memories; how to synthesize test algorithms for detection and diagnosis of FinFET specific memory defects; and how incorporating built-in self-test (BIST) infrastructures with high-efficiency test and repair capabilities can help to ensure high yield for FinFET-based memories.