This paper outlines several building blocks resulting in significant improvements to the development time of SOC’s and the systems they power. An internal bus handling transfers as packets and operating asynchronously without global control can simplify adding or removing the design objects that communicate over the bus. Multiple clock domains are possible, and an interface that is latency tolerant simplifies layout and timing issues. Design modifications can be implemented more quickly, allowing a family of SOC’s to rapidly evolve from a single IC.