Signal integrity (SI) issues, such as crosstalk delay and noise, are significant challenges for system-on-chip (SoC) designs at 130 nm and below. SI effects must be addressed prior to the final stages of physical design, or unpredictable timing-closure iterations, tapeout delays, chip failures, poor manufacturing yield—or all of the above—are likely to result. Fortunately, several years of experience with SI at very deep submicron geometries have led to efficient methodologies throughout the design flow for preventing, detecting and fixing SI effects.

This Synopsys Professional Services white paper focuses on the design best practices of applying an SI-aware flow throughout the design cycle to achieve an SI-clean tapeout in the shortest amount of time. The paper focuses on advanced techniques that have proven effective in achieving SI closure on real chips.