Design of Adaptive Fir Filters with FPGA
In this paper, we describe both LMS and RLS adaptive filtering algorithms and how they are implemented as logic blocks, not soft blocks. Mapping the logic blocks to recent DSP-specific FPGAs is also discussed. This paper is organized as follows. In the next section, basic fixed-point fraction-based arithmetic circuits for DSP are described with their bit-accurate Matlab codes. One may easily translate these Matlab codes into the equivalent HDL (verilog or VHDL) codes. In the following three sections, the LMS filtering algorithm, a bit-accurate Matlab code for LMS algorithm, and an example of VHDL code for LMS circuit are described. In the following section, the RLS filtering algorithm is briefly described. In the following section, a Matlab code for RLS algorithm is described. In the following section, FPGA implementation is discussed. Finally, concluding remarks are made in the last section.
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