As process sizes continue to shrink, mixed-signal designers are faced with an increasing number of design challenges that impact design closure. Shrinking feature sizes, finer line widths, longer interconnect and more routing layers enable more functionality packed onto a chip. With the increase in functionality, these advanced mixed analog/digital systems-on-chip (AMS SoC) designs push the technology envelope with higher clock frequencies, lower power supply voltages and increased power consumption. All this means that there is a large increase in noise sources in these designs; yet high frequency signals must run reliably in spite of all these noise sources. Problems can be dealt with effectively by employing high-performance, high-capacity, transistor-level tools that uncover signal integrity problems prior to silicon

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