As today’s mixed-signal SoC designs continue to increase in complexity, functional verification methods are rapidly evolving. Now more than ever, new, more efficient methods of verification must be explored and adopted in order to keep up with the growing demands of SoC design. Historically, entire designs were represented by a single set of transistor-level schematics, with each individual component, as well as the entire design itself, being functionally verified using a digital gate-level and or analog transistor-level simulator. In today’s SoC designs, the necessity to incorporate reusable IP from multiple sources requires that both VHDL and Verilog modeling languages must be supported in the simulation environment. To efficiently address this requirement, functional verification must now take place in a single kernel simulation environment, with the ability to trace simulation results back to appropriate source code line in Verilog or VHDL. Additionally, there must be a means by which to co-simulate sensitive analog functions using traditional SPICE and advanced analog RF algorithms. There are also the emerging standard analog and mixed-signal functional modeling languages VHDL-AMS (IEEE 1076.1), Verilog- A, and Verilog-AMS. These languages are becoming popular as alternatives to the traditional means of drawing transistor-level schematics to enter analog and mixed-signal types of components. This paper will explore the incorporation of analog and mixed-signal HDLs into an SoC design flow.

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