Delay-Safe False Paths
Engineers enter false paths on a design for a variety of reasons. A path may be specified false because it is between two asynchronous clock domains, or because the path originates from a static register whose value never changes, or because the path is a timing don’t-care. This paper focuses on paths that are specified false because the engineer believes the combination of logic values required to sensitize the path is not possible, based on the functionality of his or her design. It is important that an engineer consider, not just the functionality of the chip, but also circuit delay, when determining whether or not a path is sensitizable.
When a delay-safe false path is dynamically sensitizable, there will always exist a path through a control input that is a true path with delay greater than or equal to the dynamically sensitizable false path. For this reason, delay-safe false paths never mask a real timing problem on the chip. This paper explains why delay-safe false paths are legitimate to apply throughout an implementation flow, regardless of circuit delays.
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