Debug support is a decisive success factor for systems based on complex SoCs. Depending on the target application and production volume, different solutions can be optimum. In demanding realtime applications, trace within the target system at full speed is a key requirement. The output across package pins, of the huge amount of trace data of multi-core, multi-bus SoCs, running at high frequencies, is a technical challenge and also costly. This becomes even a bigger problem, since the required SoC trace bandwidth scales with Moore’s law (more on-chip cores) and rising clock frequencies. But for package pins physical and mechanical constraints slow down the cost decrease trend. The PSI architecture circumvents this requirement and scales with the integration density and clock frequency trends.