DDR Signal Integrity Simulation Process for Intel Architecture Platforms
SI Engineers providing solutions for the DDR Interface encounter several challenges to deliver a high confidence result, due to the complexity of the interface. To take best advantage of these features, an SI Engineer has to have a thorough understanding of the interface and solid simulation strategies. This white paper covers the Simulation Goals, Preparation stage with Layout Engineers, System Architects and Specification extraction. A Simplified Timing Analysis approach is also covered with examples for DATA and COMMAND Signal Group. In Simulation Steps, the importance of validating each model is emphasized to save debug time. Several low level questions are answered based on frequently asked questions.
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