Almost everyone knows that the bulk of Dynamic Random Access Memories (DRAMs) produced end up in desktop and laptop computers. In fact, approximately ninety percent of all DRAMs are used in computers— leaving the remaining ten percent as square pegs pounded into round holes when used as off-chip memory for Systems-on-a-chip (SoCs). As the number of SoC designs requiring an interface to external memory increases, the modern DDRn SDRAM memory interface (DDR, DDR2, DDR3) offers the security of supply, high storage capacity, low cost, and reasonable channel bandwidth, but comes with an awkward interface and complicated controller issues.

Faced with the unique command structure resulting from the internal DRAM arrays, SoC designers are left with a daunting task when incorporating state-of-the-art DRAM interfaces into their design. This paper provides a brief history of the Synchronous Dynamic Random Access Memory (SDRAM), discusses design considerations for implementing a DDRn controller and PHY, and describes how a complete intellectual property (IP) solution can help speed time-to-market and reduce costs.