Critical Area Analysis and Memory Redundancy
This paper discusses the need to analyze and optimize redundancy schemes for embedded memories in SOC designs with the goal of maximizing yield while minimizing impact on chip area and test. Failure mechanisms, repair techniques, and analysis capabilities are described. Whether you are fabless, fab-lite, or an IDM, the goal of reducing a design’s sensitivity to manufacturing issues should ideally be handled by the design teams. The farther downstream a design goes, the less likely a manufacturing problem can be addressed without costly redesign. By addressing DFM problems early, when the design is still in progress, manufacturing ramp-up issues can be avoided.
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