Creating a Third Generation I/O Interconnect
This paper looks at the success of the widely adopted PCI bus and describes a higher performance next generation of I/O interconnect, called PCI Express* Architecture, that will serve as a standard local I/O bus for a wide variety of future computing platforms. Key PCI attributes, such as its usage model and software interfaces are maintained whereas its bandwidth-limiting, parallel bus implementation is replaced by a long-life, fully-serial interface. A split-transaction protocol is implemented with attributed packets that are prioritized and optimally delivered to their target. The new PCI Express Architecture comprehends a variety of form factors to support smooth integration with PCI and to enable new system form factors. PCI Express Architecture will provide industry leading performance and price/performance.
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