In an ASIC design house in the U.S., a verification engineer wanted to measure the completeness of his verification test suite using functional coverage. The VHDL testbench and design were mature, and the test suite was comprised of assembly code tests which were manually written in three man year’s of work. The engineer believed that most of the coverage was achieved, and expected to find only a few overlooked areas. The results from the functional coverage were astonishing. The engineer found that less than 20% of functional coverage was achieved, which means that a lot of expensive resources were wasted on repeated simulations that did not add value to the coverage.