If you are pushing the limits of performance and density in an FPGA, then you are also likely facing problems that threaten your design deadlines. Long place and route runtimes and repeatability of results are two common sources of anxiety.

Also, traditional FPGA tools provide a flat, push-button implementation approach—a flow that provides few clues about how to improve your design goals and even fewer opportunities to make the necessary changes.

If you can relate to these challenges, Xilinx® offers a new tool that will put you in control of your design. The PlanAhead™ hierarchical design and analysis tool allows you to employ ASIC design methodologies for complex FPGAs. PlanAhead software easily integrates into your existing flow between synthesis and place and route. You can analyze, detect, and correct many potential problems before place and route. And with its block-based incremental capabilities, you can divide and conquer your design one block at a time.

Reprinted with permission from Xcell Journal / Second Quarter 2005. Article © Xcell Journal.