Due to the corner rounding effect in litho process, it is hard to make the wafer image as sharp as the drawn layout near 2D pattern. The inevitable gap between the design and the wafer image make the 2D pattern correction complex and sensitive to the correction parameters setting. Due to the complexity of 2D pattern in random LOGIC designs combining with the small jogs created during the rule-based OPC step, engineers have spent lots of efforts to handle different 2D fragments based on their own experience. In this paper, a general method was proposed to simplify the 2D correction. The design was first smoothed and then the simulation site was shifted from the drawn layer to this new layer. The smoothed layer was used as OPC target instead of the drawn polygons with sharp corners. By using this methodology, better image quality was achievable with less turn around time when comparing to the traditional sharp-corner target approach.

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