The Xilinx® Spartan™-3E family of FPGAs targets high-volume, cost-sensitive consumer electronic applications with a density range from 100,000 to 1.6 million system gates. It offers performance and cost enhancements over the previous generation of Spartan devices, as well as a new configuration mode allowing a glueless interface to standard parallel NOR flash memories. Nearly all of the configuration pins can be used as user I/Os after configuration.

This configuration mode, known as the byte-wide peripheral interface (BPI) parallel flash mode, lets you take advantage of low-cost and high-density Intel StrataFlash 3V Memory (J3), or J3 Memory. J3 Memory uses Intel ETOX process technology with multi-level cell capability, which provides 2X the bits in 1X the space.

Reprinted with permission from Xcell Journal / Third Quarter 2005. Article © Xcell Journal.